Core engineering and protocols for Hardware Acceleration Engines.
Software implementations of FHE suffer from severe memory bandwidth starvation: ciphertexts are massive (megabytes per encrypted array), and NTT algorithms require constant memory transpose operations across memory hierarchies. FHEnc bypasses this bottleneck by deploying custom FPGA accelerators equipped with on-chip High-Bandwidth Memory (HBM2e/HBM3) delivering over 1.2 TB/s of local memory throughput.
Our FPGA RTL architecture implements deeply pipelined Barrett and Montgomery reduction units optimized for standard RNS primes. By scheduling twiddle factor reads from on-chip UltraRAM, our accelerator computes a 65,536-point NTT in under 12 microseconds, achieving a 100x performance leap over high-end 64-core server CPUs.